Atrenta to Demonstrate Power of Predictive Analysis At Dac'02 in New Orleans
SpyGlass Products Predict Downstream Problems Early in Design Cycle
SAN JOSE, Calif.--(BUSINESS WIRE)--June 3, 2002--Atrenta Inc., the
Predictive Analysis company, is offering integrated circuit designers
a unique opportunity to see first hand why leading electronic and
semiconductor companies are using its predictive analysis products
BEFORE running simulation or synthesis. At this year's Design
Automation Conference (DAC), June 10-12, 2002 in New Orleans, Atrenta
will demonstrate its SpyGlass(TM) family of predictive analysis
products. These products help predict and identify SoC
(system-on-chip) integration issues, testability issues and RTL
(register-transfer level) handover issues that normally only show up
much later in the design process. By fixing these problems early,
designers can significantly cut their SoC design time. Engineers can
see Atrenta's SpyGlass products in booth 2925 or sign up for an
in-depth demonstration in suite 4006.
Atrenta will be highlighting three new products introduced earlier
this year: SpyGlass SoC, SpyGlass DFT and SpyGlass 3.0. SpyGlass SoC
enables design teams to carefully evaluate incoming IP (intellectual
property) and internally designed RTL blocks to ensure it meets
project guidelines. In addition to hookup checks, SpyGlass SoC zeroes
in on tough issues that often cause significant delays in SoC
integration, such as race conditions, clock synchronization, set/reset
consistency and much more. This aligns all the blocks for quick
integration and eliminates schedule delays caused by inconsistent
design practices.
SpyGlass DFT focuses testability analysis at the RTL development
stage, detecting problems and guiding designers to the best possible
solutions. This proactive approach lets designers know, right from the
start, if their design is scan ready and if the required fault
coverage will be met. SpyGlass DFT pinpoints un-testable logic and
suggests changes that let designs speed through the testing process.
SpyGlass 3.0 identifies complex design problems and downstream
tool flow issues right up front at RTL creation time, resulting in
early detection of problems, fewer design iterations and early time to
market. RTL problems that cause handover issues, including timing and
layout problems, are detected early in the design cycle. SpyGlass
reports on logic depth between registers by source and destination
clock domains, snake paths that may create floorplanning and timing
issues, un-driven signals, and dead-code.
To sign up for an in-depth demonstration at Atrenta's suite,
designers should email dac@atrenta.com.
About Atrenta
Atrenta offers a new approach in accelerating the design of
complex ASICs, FPGAs, and SoCs through predictive analysis. Its
SpyGlass software is the first tool that performs detailed structural
analysis on register-transfer-level Verilog and VHDL code in order to
check for complex problems, which include coding styles, RTL-handoff,
design re-use, clock/reset requirements, and much more. Its
breakthrough and innovative "look-ahead" capability incorporates a
fast-synthesis engine, logic evaluator, and testability technologies.
Atrenta has over forty-five customers, such as Agere, Agilent, Apple,
ARM, Canon, Compaq, Fujitsu, Hitachi, LSI Logic, Motorola, National
Semiconductor, NCR, Nortel and Olympus, who are using SpyGlass to
achieve shorter overall design cycles, increased design productivity
and lower costs. Atrenta is headquartered in San Jose, California,
with European headquarters in Swindon, England, a research and
development center in India, and sales and support distributors in
Japan, Taiwan, India and Singapore. For further information, visit the
Atrenta website at http://www.atrenta.com or call 1-866 ATRENTA.
Note to Editors: Atrenta and SpyGlass are trademarks of Atrenta
Inc. All other trademarks belong to their respective owners.
Contact:
Atrenta
Mona Singh, 408/467-4248
mona@atrenta.com
or
Atrenta PR Counsel
Paula Jones, 650/967-3711 (Editorial)
paula@newiic.com
